The aim of the project is to familiarize on the using of Intel Quartus Prime for the digital system design and the ModelSim for the simulation. Within the Quartus Prime software, digital circuitry is designed and modeled using a hardware description language (HDL) called VHDL. VHDL is an industry standard programming language for quickly and easily representing complex digital circuits at various levels of abstraction. The VHDL code is compiled and simulated using ModelSim software, allowing the design’s performance is validated. The project basically involves development of various HDL based circuits in two sections as follows;
To develop the VHDL code that will function as a 4-bit Odd Parity coding system, as represented in schematic/block diagram which is shown in the requirement file. This will includes both the Odd parity ENCODER and the Odd parity DECODER.
Adapting the VHDL code, developed in Section 1, and writing the code for a 7/4 Hamming coding system where 4-bits of parallel input data (D1-4) are encoded into 7-bit code-words (C1-7).
A parity bit is a verification bit that is added to just a block of methods to find errors. It’s being used to validate the data’s integrity. The parity bit is assigned a value of 0 or 1, which determines whether the number of 1s in the message block is even as well as odd depending upon the nature of parity. Comparability check is only useful for detecting single bit errors.
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LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Section1PA IS GENERIC( io : INTEGER := 4; –this is the number of bits odd_parity : STD_LOGIC := ‘1’); –this is the odd res_parity type PORT( io_put : IN STD_LOGIC_VECTOR(io-1 DOWNTO 0); –this is the data input res_parity : OUT STD_LOGIC); –this is the result data for res_parity END Section1PA; ARCHITECTURE Parity OF Section1PA IS SIGNAL intermediate_parity : STD_LOGIC_VECTOR(io DOWNTO 0); — this is the intermediate results for the res_parity BEGIN –res_parity calculation Parity intermediate_parity(1) <= odd_parity; –this is the results for the odd parity_logic: FOR i IN 1 to io-1 GENERATE intermediate_parity(i+1) <= intermediate_parity(i) XOR io_put(i); –XOR for the resuts of the next input END GENERATE; res_parity <= intermediate_parity(io); –the end and the final results END Parity; |
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library IEEE; use IEEE.std_logic_1164.all; entity Section1PB is port ( odd_input : in std_logic; — Odd input odd_output : out std_logic; — Odd output results odd_parity : in std_logic_vector(3 downto 0)); end entity; architecture odd_parity_acrchitecture of Section1PB is signal variation : std_logic; begin variation <= odd_parity(0) xor odd_parity(1) xor odd_parity(2) xor odd_parity(3); odd_output <= variation xor odd_input; end odd_parity_acrchitecture; |
The goal here is to make the maximum count of 1s odd. Recognize the same information signal from earlier. “010”. The parity bit in this case will be….complete the sentence. 0! The message signal already has an odd number of 1s. When the message arrives at its destination, we only need to check the parity bit to see if it is odd or even. Compare that to what we knew at the transmitting end. And we can tell if there is an error. If we have four bits, we have a four-bit odd parity transformer. The production odd parity bit is now determined by four input bits, part A and part, B, C, and D. Using the Sum-of-Products method, solve the truth table for all cases where P is 1. We can also solve for the output using K-maps.
Hamming code not only detects bit errors, but also recognizes where what bit is incorrect because it can be corrected. As a result, hamming code is also known as error detecting and correct decision code. It is used to detect and correct a single bit error as well as a double bit error. Along with its simplicity, hamming code is widely used throughout computing memory, data compression, and other telecommunications applications.
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY Section2PA IS PORT(input : IN BIT_VECTOR(0 TO 3); –d1 d2 d3 d4 output : OUT BIT_VECTOR(0 TO 6)); — d1 d2 d3 d4 p1 p2 p3 END Section2PA; ARCHITECTURE Hammer OF Section2PA IS SIGNAL p1, p2, p3 : BIT; BEGIN p1 <= (input(0) XOR input(1)) XOR input(3); p2 <= (input(0) XOR input(2)) XOR input(3); p3 <= (input(1) XOR input(2)) XOR input(3); output(4 TO 6) <= (p1, p2, p3); output(0 TO 3) <= input(0 TO 3); END Hammer; |
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library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use IEEE.STD_LOGIC_arith.all; ENTITY Section2PB IS PORT (clk : IN STD_LOGIC; input : IN STD_LOGIC_VECTOR(1 downto 0); output : OUT STD_LOGIC); END Section2PB; ARCHITECTURE behav of Section2PB is SIGNAL in : STD_LOGIC_VECTOR(1 downto 0):= (others => ‘0’); SIGNAL out : STD_LOGIC_VECTOR(3 downto 0):= (others => ‘0’); SIGNAL res : STD_LOGIC_VECTOR(5 downto 0):= (“10000”); BEGIN PROCESS BEGIN WAIT UNTIL (clk’EVENT AND clk = ‘1’); res <= res (0) & res(5 DOWNTO 1); in <= input; IF(res(5)=’1′) THEN out <= in & (<); ELSE out <= out(3-1 DOWNTO 0) & ‘0’; END IF; END PROCESS; output <= out(3); END behav; |
The dataword is fed into the encoder circuit, that further performs XOR operational processes on the given set of data word, generating the required parity bits from the parity bit generator. The code word is made up of parity and data bits. A hamming code encoder circuit for such a 4-bit data word. Following this circuit pattern, we can design a hamming code encoder circuit for such a 7-bit data word, which is then implemented in the DSCH tool.
A hamming code decoder circuit for a 4-bit data word. This same circuit is made up of an analyser bit generator, three to eight decoders, and XOR gates. The code word is implemented as an input throughout this circuit, and the activities relating are generated either by checker bit generator. Those same bits are given to the decoder, which enables the XOR gate with the error.It should either be detected or corrected, depending upon that correction algorithm.
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